This invention relates to stacked chip (stacked die) packages.
Increasingly, the semiconductor industry requires that packages have greater functionality in increasingly thin, small and compact package structures. There has been rapid progress in increasing the density of semiconductor devices in packages. In one approach, stacked chip scale package (SCSP) have been developed. These packages include two chips (or usually more than two chips), stacked on a substrate which has a chip mount area on the front surface and a solder ball pad area on the back surface. The chips are mounted using adhesive materials, and are electrically connected with the substrate using wire bonds which connect bond pads on the chip and bond fingers in a circuit pattern on the front surface of the substrate. Solder balls are mounted on the ball pads on the back surface of the substrate, for interconnection of the package with, for example, a motherboard. The die (chips), the wires, and other features on the front side of the substrate are encapsulated with an encapsulation material.
These features of such a conventional SCSP are shown diagrammatically by way of example in FIG. 1, in sectional view. The package includes a package substrate having a die mount region on a front surface, and second level interconnect solder ball pads on a back surface. The illustrated package includes six die (semiconductor chips), including two bare silicon spacer die, stacked and mounted on the die mount region of the front surface of a substrate.
The die are electrically interconnected to the substrate by wire bonds connecting bond pads on the respective die (die pads) to bond sites on a circuit pattern on the front surface of the substrate. Solder balls are mounted on ball pads on the back surface of the substrate, for second level interconnection of the package with, for example, a motherboard.
The lowermost (first) active die in the stack is affixed on a die mount region of the front surface of the substrate using an adhesive material, which may be a die attach epoxy, for example, or an adhesive film. A second active die is affixed onto the first die, again using an adhesive. A first spacer is affixed onto the first die, using an adhesive; the spacer may be, for example, a “dummy” die, cut from a silicon wafer having no circuitry, or it may be a glass chip, for example. A third active die is stacked over the spacer, and affixed using an adhesive. The third active die is as wide as or wider than the second active die, and the spacer is employed between the second active die and the third active die, so that the marginal parts of the third active die overhang the wire loops connecting the second active die to the substrate. The spacer must have a footprint selected to prevent interference by the spacer with the connection of the wire loops with the die pads, and must have a thickness selected to provide relief for the wire loop height (plus some tolerance). A second spacer is affixed onto the third active die, using an adhesive; this spacer may also be, for example, a “dummy” die. A fourth active die is stacked over the second spacer, and affixed using an adhesive. The fourth active die in this example is wider than the third active die, and the second spacer is employed between the third active die and the fourth active die, so that the marginal parts of the third active die overhang the wire loops connecting the third active die to the substrate. As noted above, this package when complete includes six-stacked chip, all of which contribute to the overall thickness of the package, but only four of the die have an electrical function. Accordingly, in such a conventional package the electronic density of the package, and the thinness profile, are compromised.